The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a method of manufacturing a semiconductor device having an improved element isolation step.
As is known, in a semiconductor device manufacturing process, an element isolation region (field insulating film) is formed to isolate the element region of the semiconductor substrate from any other region thereof. In particular, along with the high packing density and the high integration of recently developed semiconductor devices, there has arisen a demand to establish a micropatterning technique for forming a smaller element isolation or field region.
The selective oxidation process has been conventionally used as an element isolation method. However, according to this selective oxidation process, a field oxide film extends into the element region to form a so-called bird's beak. Therefore, this method is not suitable for micropatterning.
In consideration of the above situation, the present inventors have already proposed a proper element isolation method suitable for micropatterning the element. An example will be described with reference to FIGS. 1A to 1F wherein this method is applied to the manufacture of a MOS transistor.
(i) As shown in FIG. 1A, a p.sup.- -type silicon substrate 1 of high resistance is thermally oxidized in a wet oxygen atmosphere at a temperature of 1,000.degree. C. to grow a thermal oxide film (insulating film) 2 to a thickness of 5,000 .ANG.. A photoresist film is coated to cover the entire surface and is patterned by photoengraving to form a resist pattern 3.
(ii) Boron is non-implanted as a field stopper impurity at an acceleration voltage of 200 keV and a dose of 1.times.10.sup.13 /cm.sup.2 by using the resist pattern 3 as a mask, so that p.sup.+ -type inversion preventive layers 4 are selectively formed in the silicon substrate 1 through the thermal oxide film 2. An aluminum film is deposited by vacuum deposition to cover the entire surface to a thickness of 2,000 .ANG.. The aluminum film is separated into aluminum film portions 5a on the resist pattern 3 and aluminum film portions 5b on the thermal oxide film 2, as shown in FIG. 1B. The resist pattern 3 is removed and the aluminum film portions 5a are lifted off, so that the aluminum film portions 5b are left in a propective element isolation region on the thermal oxide film 2 (FIG. 1C).
(iii) The thermal oxide film 2 is selectively etched by reactive ion etching (RIE) using the remaining aluminum film portions 5b as masks to form a field oxide film (element isolation region) 6. Thereafter, the aluminum film portions 5b on the field oxide film 6 are removed (FIG. 1D).
(iv) Thermal oxidation is performed on an exposed portion of the silicon substrate 1 to form an oxide film of 400 .ANG. thickness which can serve as a gate oxide film. Subsequently, a phosphorus-doped polycrystalline silicon film is deposited to cover the entire surface to a thickness of 4,000 .ANG.. Patterning by the RIE method is performed to form a gate electrode 7. The oxide film is etched using the gate electrode 7 as a mask, thereby forming a gate oxide film 8 (FIG. 1E). Arsenic is diffused using the gate electrode 7 and the field oxide film 6 as masks, so that n.sup.+ -type source and drain regions 9 and 10 are formed in the silicon substrate 1. Thereafter, a CVD-SiO.sub.2 film 11 is deposited to cover the entire surface and is patterned to form contact holes. An aluminum film is deposited and patterned to form aluminum wiring layers 12 and 13, thereby completing preparation of a MOS semiconductor device (FIG. 1F).
However, this conventional method presents the following problem. As shown in FIG. 2A, a thermal oxide film 14 is grown, a phosphorus-doped polycrystalline silicon film 15 is deposited, and a resist film 16 is formed all after the field oxide films 6 are formed. In this case, the resist film 16 has portions formed on the edges of the polycrystalline silicon film 15 which respectively correspond to edges A of the field oxide films 6. These portions have a thickness greater than the remaining portions of a resist film 16. Therefore, when the resist film 16 is developed after exposure, residual resist portions 16' tend to be left at the edges of the field oxide film 6. Excessive development must be performed to remove these resist portions 16'. Therefore, controlling the size of the resist pattern is very difficult. In addition, when the thermal oxide film 14 and the phosphorus-doped polycrystalline silicon film 15 are formed after the field oxide film 6, the thickness (t.sub.1) of the flat portion of the polycrystalline silicon film 15 is 4,000 .ANG., but the thickness (t.sub.2) of the stepped portion at each of the edges of the field oxide film 6 is about 9,000 .ANG.. For this reason, when the polycrystalline silicon film 15 is etched by the RIE method to micropattern the gate electrode to be formed, etching occurs only vertically downward from the surface. As a result, as shown in FIG. 3B, residual polycrystalline silicon portions 17 are left at the stepped portions of the field oxide film 6. When a plurality of MOS transistors are formed in a single element region, gate electrodes of the resultant MOS transistors are short-circuited because of the presence of these residual polycrystalline silicon portions 17.
In addition to these disadvantages, when the CVD-SiO.sub.2 film 11 and then the aluminum wiring layers 12 and 13 are formed after the field oxide film 6, poor coverage occurs at the shoulders 18 of the steep stepped portions at the edges of the field oxide film 6, so the aluminum wiring layers 12 and 13 tend to be disconnected, as shown in FIG. 4, resulting in inconvenience.